As conventional MOSFETs channel lengths are scaled down below 100 nm for improved performance and packing density, the gate oxide thickness is also scaled below 3 nm. Due to this aggressive scaling short channel effects (SCEs) like threshold voltage roll-off & gate leakage current play a major role in determining the performance of scaled devices. The double gate (DG) MOSFETs are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling [1]. On the other hand, nanotechnology has achieved significant progress in recent years, fabricating a variety of nanometer scale devices, e.g., molecular diodes and Carbon Nanotube field effect transistors (CNFETs). This has provided new opportunities for VLSI circuits to achieve continuing cost minimization and performance improvement in a post-silicon-based-CMOS-technology era. Carbon Nanotube based FET devices are getting more and more importance today because of their high channel mobility, improved voltage characteristics & have been considered as a replacement for future semiconductor devices due to high mobility, low defect structure, and intrinsic nanometer scale of Carbon Nanotubes (CNTs) [8]. So by changing the material like polysilicon with Carbon Nanotube the short channel effect can be reduced. The attempt has been made to change the material exist in Silvaco''s TCAD library to Carbon Nanotube environment for model MOSFET-like DG CNFET device. This study present VI characteristic of DG CNFET to achieves its objectives [2]. Simulation work on DG CNFET is carried out to investigate the dependence of I-V characteristics on various polysilicon (as Carbon Nanotube channel) thickness, doping level on polysilicon (as Carbon Nanotube channel) and mobility defined on polysilicon to be Carbon Nanotube environment. Now by comparing the characteristics of DG MOSFET characteristics with DG CNFET characteristics
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